IHT-Soft

IP we can provide you with

Our team provides list of IP blocks that help our customers to build proven subsystems for their successful projects.

All of our IP are highly configurable to meet customer needs and provide debug access with great level of visibility.

IP provided with set of deliverables and guidelines to ensure seamless integration into the design flow including:

• Behavioral model to ensure functionality
• Functional model ready for AMS simulation
• Frontend deliverables - RTL integration wrappers and examples, timing libraries and constraints
• Backend deliverables - LEF, timing constraints, power libraries and integration guidelines
• Signoff deliverables - GDSII, LVS and extracted netlists as well as DRC and LVS reports

Custom CCD signal processing subsystem

CCD sensors used in different areas including consumer, scientific, industrial and biomedical applications. Combining ultimate sensitivity with low readout noise made the CCD sensor a staple in the imaging sector for over 30 years.

There is growing demand for CCD sensors to improve their sensitivity over a broader wavelength range as well as for traditional optical sense. Today, significant advances are being made to improve the spectral response performance and need in custom signal processing blocks to ensure low noise level for overall solution.

Highly customizable IP subsystem designed to work with most CCD sensors. Several subsystem blocks are available for our customers. To ensure customer success our design team provide configuration and integration services.

• Input channel: CCD Readout Channel with LPF

Charge Coupled Device (CCD) readout channel. It provides summation of CCD output signal and predefined offset voltage. Adder output signal is processed by low-pass active Butterworth filter. The filter provides a maximally flat passband response which makes its transfer function linear. The filter allows to switch cutoff frequency from 50 kHz to 10 MHz. IP is available as configurable hard macros in 180 nm bulk-Si process.

Table 1 parameters

• Input channel: CCD Readout Channel with CDS

IP implements a Charge Coupled Device (CCD) readout channel which contains Correlated Double Sampling (CDS) block. The CDS is a noise reduction technique which provides subtraction of black level from color level for each pixel. The CDS output signal is processed by a PxGA (pixel gain amplifier). The PxGA is a linear-in-dB variable gain amplifier with predefined gain value for various color (or different parts of sensor) pixels. IP contains voltage reference for restore input common mode level. IP is available as configurable hard macros in 180 nm bulk-Si process.

Table 2 parameters

• Processing: CCD Signal Processing Block

IP implements a signal processing chain for various Charge Coupled Device (CCD) readout channels. Block is capable to handle at least 2 channels selected by input multiplexer. The signal processing chain contains Variable Gain Amplifier (VGA) which has linear-in-dB gain transfer function. An output signal from VGA is digitized by high speed Analog-to-Digital Converter (ADC), which has mixed-signal feedback path for black level correction and noise mitigation. The ADC output data has both serial and parallel format. Mixed signal feedback path contains clamp level register, comparator, digital filters and Digital-to-Analog Converter (DAC). IP contains two highly stable voltage references for ADC and DAC and internal components. IP is available as configurable hard macros and RTL model for digital part in 180 nm bulk-Si process.

Table 3 parameters

• Control: CCD Readout Control and Status Block

IP provides control of Charge Coupled Device (CCD) readout channels and its processing block. IP contains VGA and PxGA gain registers with multiplexed output for setup PxGA gain separately for different color pixels. IP provides control of color steering with specialized register for color steering mode. Voltage reference block and two DACs are used for offset voltage setup for CCD readout channels. IP supports data transmission via SPI bus and has integrated SPI controller. IP is available as configurable hard macros and RTL model in 180 nm bulk-Si process.

Table 4 IP parameters